A PDF shown off by Sun Microsystems leaked onto the net yesterday detailing Dunnington: Intel's new hex-core CPU built on its 45nm technology. In contrast to Intel's quad core designs, It features a single die with specially designed Penryn cores that has pairs sharing 3MB of cache, instead of the usual six.
These are then all bolted onto a massive 16MB of shared L3 cache and also connected to a 1,066MHz bus interface. The L3 cache is there to compensate for the latency and bandwidth stretched front side bus - six cores competing for access should seriously stress this interlink and its access to main memory and the rest of the system. This will be the last core increase until Nehalem arrives at the very end of this year with up to eight cores.
Further details of Dunnington include a TDP of around 130W and the inclusion of the latest SSE4 instructions, however it will be Xeon socket mPGA604 and will fit into the new Caneland platform but will be pin compatible with the current Tigerton.
No specific desktop use has been outlined, but that's not to say Intel hasn't gone down this path before: the first Pentium 4 Extreme Editions used the Galatin cored Xeon chip which was built on the 130nm design and featured 512KB L2 cache and 2MB L3 cache. While there's no reason for Intel to do this given the fact it's currently leading the performance race, was there really need for the QX9770 either?
In addition, Nehalem's platform was again given a bit more detail - despite the fact that it will effectively contain "the north bridge" as it includes a memory controller, Intel is still using a pair of chipsets in its product design. The I/O Hub will only offer the PCI-Express lanes and talk to up to two CPUs but it won't act as the mediator between them because Nehalem includes multiple QuickPath direct interconnects just like AMD's HyperTransport technology.
Included are also SPEC results that show off Nehalem-EP as one meaty beast, pulling quite a lead over the current 3.2GHz 1,600MHz FSB Harpertown server products.
Six cores - great for servers but useful for desktops? What will AMD compete with? Let us know your thoughts, in the forums.
These are then all bolted onto a massive 16MB of shared L3 cache and also connected to a 1,066MHz bus interface. The L3 cache is there to compensate for the latency and bandwidth stretched front side bus - six cores competing for access should seriously stress this interlink and its access to main memory and the rest of the system. This will be the last core increase until Nehalem arrives at the very end of this year with up to eight cores.
Further details of Dunnington include a TDP of around 130W and the inclusion of the latest SSE4 instructions, however it will be Xeon socket mPGA604 and will fit into the new Caneland platform but will be pin compatible with the current Tigerton.
No specific desktop use has been outlined, but that's not to say Intel hasn't gone down this path before: the first Pentium 4 Extreme Editions used the Galatin cored Xeon chip which was built on the 130nm design and featured 512KB L2 cache and 2MB L3 cache. While there's no reason for Intel to do this given the fact it's currently leading the performance race, was there really need for the QX9770 either?
In addition, Nehalem's platform was again given a bit more detail - despite the fact that it will effectively contain "the north bridge" as it includes a memory controller, Intel is still using a pair of chipsets in its product design. The I/O Hub will only offer the PCI-Express lanes and talk to up to two CPUs but it won't act as the mediator between them because Nehalem includes multiple QuickPath direct interconnects just like AMD's HyperTransport technology.
Included are also SPEC results that show off Nehalem-EP as one meaty beast, pulling quite a lead over the current 3.2GHz 1,600MHz FSB Harpertown server products.
Six cores - great for servers but useful for desktops? What will AMD compete with? Let us know your thoughts, in the forums.
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