Intel announced today that it has made scaled Floating Body Cell memory with its High-k and Metal Gate 45nm technology that could mean a new era of super dense cache cells in CPUs and other applications.
The company currently has devices with gate lengths measuring down to 30nm, but also cites the positive simulated prediction for making a 15nm and 10nm nodes.
FBC is a candidate for increased memory density by a factor of three or four times compared to standard SRAM cache in the same area, which uses six transistors. Instead, FBC uses just "one" capacitor (with voltages on both sides to store the charge) under a single 45nm Metal Gate on an incredibly thin 22nm, ultra low voltage Silicon On Insulator (SOI) substrate. This "planar device" is two generations ahead of what Intel showed off in 2006 - that particular demonstration used two gates and no SOI.
Intel is still working with single cells to optimise its process, however future plans intend to look at large arrays of FBC cache.
While it announced its 45nm High-k and Metal Gate technology last year, this year it is announcing Strain-Enhanced Transistors on top of this. By straining the transistors Intel can achieve better performance and energy efficiency - the process flow is made with a "Gate Last" technique that incorporates NMOS and PMOS transistor strain enhancements. This process also now includes the use of cheaper 193nm dry lithography to high density 45nm designs without adding extra time consuming masking layers.
The strain allows a PMOS drive current drop by 50 percent and NMOS by 12 percent offering an overall average power saving of 32 percent. By doing the gate last, Intel can independently control the compressive strain to the p-channel and temple strain to the n-channel.
Intel hasn't explicitly said how this technology translates into real world products, but having the technology at its disposal could see it potentially being used in a lot of products in the future.
Care to throw your technical hat into the mix? Let us know your thoughts in the forums.
The company currently has devices with gate lengths measuring down to 30nm, but also cites the positive simulated prediction for making a 15nm and 10nm nodes.
FBC is a candidate for increased memory density by a factor of three or four times compared to standard SRAM cache in the same area, which uses six transistors. Instead, FBC uses just "one" capacitor (with voltages on both sides to store the charge) under a single 45nm Metal Gate on an incredibly thin 22nm, ultra low voltage Silicon On Insulator (SOI) substrate. This "planar device" is two generations ahead of what Intel showed off in 2006 - that particular demonstration used two gates and no SOI.
Intel is still working with single cells to optimise its process, however future plans intend to look at large arrays of FBC cache.
While it announced its 45nm High-k and Metal Gate technology last year, this year it is announcing Strain-Enhanced Transistors on top of this. By straining the transistors Intel can achieve better performance and energy efficiency - the process flow is made with a "Gate Last" technique that incorporates NMOS and PMOS transistor strain enhancements. This process also now includes the use of cheaper 193nm dry lithography to high density 45nm designs without adding extra time consuming masking layers.
The strain allows a PMOS drive current drop by 50 percent and NMOS by 12 percent offering an overall average power saving of 32 percent. By doing the gate last, Intel can independently control the compressive strain to the p-channel and temple strain to the n-channel.
Intel hasn't explicitly said how this technology translates into real world products, but having the technology at its disposal could see it potentially being used in a lot of products in the future.
Care to throw your technical hat into the mix? Let us know your thoughts in the forums.
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