ARM has officially announced its first official 64-bit chip design, the ARMv8-based Cortex-A50 family.
Designed around AArch64, an energy-efficient 64-bit ARM architecture implementation, the new design is capable of running 32-bit or 64-bit code - much like a 64-bit x86 chip - in parallel. As a result, those looking to make the move to a Cortex-A50 chip can first port their operating system across to the 64-bit architecture while running 32-bit applications on top, then gradually port across the applications as well.
To help things along, ARM claims to have improved the efficiency of the AArch32 execution state over the previous ARMv7 instruction set architecture, meaning the chip can run 32-bit code faster than its predecessors. The new architecture also introduces more advanced Single Instruction Multiple Data (SIMD) capabilities, hardware cryptography acceleration, increased register files, flexible addressing modes, tagged pointer support, 64K data pages, enhanced cache management and improved floating-point performance.
The new Cortex-A50 family comprises two chips: the Cortex-A53 and the Cortex-A57. The former is aimed squarely at creating long-life smartphones and tablets, offering improved energy efficiency over existing ARMv7 chips like Nvidia's Tegra 3 and Samsung's Exynos 5 while providing improved performance. The Cortex-A57, meanwhile, offers a more powerful chip for devices where performance is key - but can be combined with Cortex-A53 cores in ARM's 'big.LITTLE' configuration to provide the best of both worlds.
The Cortex-A53 design includes between 8-64K I- and D-caches along with 128KB to 2MB of L2 cache, and supports 32-bit or 64-bit code with virtual 40-bit physical addressing. The Cortex-A57, meanwhile, features fixed 48K I-cache and 32K D-cache and between 512KB and 2MB of L2 cache, along with virtual 44-bit physical addressing.
Performance gains are impressive: based on the same clockspeed, ARM claims that the Cortex-A57 achieves up to 30 per cent higher performance than the Cortex-A15 ARMv7a design, extending to 50 per cent when constructed on a 20nm rather than 28nm process. That performance boost is based, ARM explains, on 32-bit code executing in AArch32 mode, with further performance gains expected when code is recompiled to take advantage of the chip's native AArch64 mode.
How long it will take ARM's customers to start deploying ARM Cortex-A50-based chips, however, remains to be seen. With many still working on the switch to the Cortex-A15 family, we're not expecting to see anything in the immediate future.
Designed around AArch64, an energy-efficient 64-bit ARM architecture implementation, the new design is capable of running 32-bit or 64-bit code - much like a 64-bit x86 chip - in parallel. As a result, those looking to make the move to a Cortex-A50 chip can first port their operating system across to the 64-bit architecture while running 32-bit applications on top, then gradually port across the applications as well.
To help things along, ARM claims to have improved the efficiency of the AArch32 execution state over the previous ARMv7 instruction set architecture, meaning the chip can run 32-bit code faster than its predecessors. The new architecture also introduces more advanced Single Instruction Multiple Data (SIMD) capabilities, hardware cryptography acceleration, increased register files, flexible addressing modes, tagged pointer support, 64K data pages, enhanced cache management and improved floating-point performance.
The new Cortex-A50 family comprises two chips: the Cortex-A53 and the Cortex-A57. The former is aimed squarely at creating long-life smartphones and tablets, offering improved energy efficiency over existing ARMv7 chips like Nvidia's Tegra 3 and Samsung's Exynos 5 while providing improved performance. The Cortex-A57, meanwhile, offers a more powerful chip for devices where performance is key - but can be combined with Cortex-A53 cores in ARM's 'big.LITTLE' configuration to provide the best of both worlds.
The Cortex-A53 design includes between 8-64K I- and D-caches along with 128KB to 2MB of L2 cache, and supports 32-bit or 64-bit code with virtual 40-bit physical addressing. The Cortex-A57, meanwhile, features fixed 48K I-cache and 32K D-cache and between 512KB and 2MB of L2 cache, along with virtual 44-bit physical addressing.
Performance gains are impressive: based on the same clockspeed, ARM claims that the Cortex-A57 achieves up to 30 per cent higher performance than the Cortex-A15 ARMv7a design, extending to 50 per cent when constructed on a 20nm rather than 28nm process. That performance boost is based, ARM explains, on 32-bit code executing in AArch32 mode, with further performance gains expected when code is recompiled to take advantage of the chip's native AArch64 mode.
How long it will take ARM's customers to start deploying ARM Cortex-A50-based chips, however, remains to be seen. With many still working on the switch to the Cortex-A15 family, we're not expecting to see anything in the immediate future.
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