Taiwan Semiconductor (TSMC) has announced it is to begin offering a 3D stacked chip technology, dubbed Wafer-on-Wafer (WoW), to its customers, along with the promise of a 7nm+ process this year and 5nm for 2019.
As semiconductor manufacturers find it increasingly difficult to continue adhering to Intel co-founder Gordon Moore's self-fulfilling law that the number of transistors in a bleeding-edge integrated circuit tends to double every 18 months - just ask Intel, which has once again pushed back its 10nm process node after years of biennial shrinkages - interests have turned to other methods of achieving the same goal. In storage, layered dies have become commonplace - and now TSMC wants to offer the same functionality to other semiconductors.
Announced in partnership with Cadence Design Systems, TSMC's Wafer-on-Wafer (WoW) packaging technology builds on the company's existing Chip-on-Wafer-on-Substrate (CoWoS) and Integrated Fan-Out (InFO) 3D chip manufacturing techniques, offering a simplified means of doubling the number of transistors in a given package without also doubling its footprint. The technique works exactly as the name suggests: Two traditional wafers are created, then bonded together with the upper wafer flipped so that the last layer to be manufactured - known as the back-end of line (BeOL) layer - is touching its equivalent on the lower wafer. Components on both wafers are then connected to the grid array on the chip's final package using through-silicon vias (TSVs).
'The [TSMC 3D] packaging technologies can be combined, using WoW to join wafers, and then putting them on an interposer, creating a 2-die cube,' partner Cadence explains in a blog post which published prior to TSMC's announcement during the company's annual conference this week. 'In fact, it is possible to vertically stack more than two wafers if all except the very bottom one have TSVs to get the signals between the layers.'
'The new WoW reference flow complements our established InFO and CoWoS chip integration solutions and gives customers more flexibility to use advanced packaging techniques,' added Suk Lee, TSMC senior director for the Design Infrastructure Marketing Division, in a joint statement with the company. 'Cadence’s strong support for our packaging technologies is instrumental in enabling our mutual customers to achieve the benefits our solutions have to offer.'
During the same event TSMC confirmed that it is launching an enhanced 7nm process node, dubbed 7nm+, following its primary 7nm node hitting volume production, and plans to release its first 5nm parts in early 2019.