AMD shares some details on future CPUs

July 27, 2007 | 14:20

Tags: #45nm #64 #64nm #6mb #analyst #barcelona #cache #core #day #displayport #hypertransport #l2 #l3 #opteron #phenom #quad #r700 #server #shanghai #x2 #x4

Companies: #amd

AMD's Technology Analyst Day was held yesterday in San Jose, and a few interesting revelations about the company's future were given to the press.

Barcelona yields are ahead of what was planned according to AMD, and the CPUs are still on track for a Q3 2007 production. Barcelona represents about a 50 percent progress through AMD's second generation Opteron platform - the 45nm Shanghai core due late next year will be the last of the current generation. Shanghai will still feature 512KB L2 cache per core, but will increase the 2MB shared L3 cache to a 6MB shared L3 cache. It will also come with an improved IPC (instructions per clock cycle).

AMD intends to start the third generation of its Opteron platform in the middle of 2009, with the launch of a new core, codenamed Sandtiger. This is still a server chip, but a desktop version will undoubtedly be released in whatever happens to be AMD's socket of choice at that time. The chip will feature DirectConnect 2 technology, HyperTransport 3.0, four HT links, PCI-Express 2.0 and DDR3 as well as a G3 memory extender (G3MX).

AMD is still hot (or not, as the case may be) for "performance per watt" and energy efficiency computing across the board, stating that PC buyers are now more energy conscious than ever before. Indeed, here at bit-tech we test power consumption in many of our hardware reviews as well. It may appear to be a bit slow of late with product releases, but (without citing Intel's previous commitment to the same routine) AMD is committed to releasing a new core and then new silicon technology (65nm, 45nm, 32nm, etc.) in alternate years.

There is currently no indication on the amount of cores Sandtiger will have, but another of the enhancements is a new IOMMU on chip for security and performance. AMD has hinted at something like this for a while, and it makes sense given that the current situation requires on-board devices to go through the chipset and CPU before getting to main memory.

This hinders performance for a graphics card's DMA access for example, where in comparison on Intel systems, the northbridge just handles all the memory requests from CPU and the devices, cutting out one of the stops. In addition, it means a consolidation of all the memory addresses thus making it easier to manage a system's real and virtual resources.

By having it all on chip allows for a much faster and lower latency system, but it also limits what you can potentially do if buying a CPU gets you a whole subsystem on-chip. In some respects, it's a case of putting all your eggs in one basket: it worked with the Athlon 64, but was that only because Intel's Pentium 4 was so incredibly poor. Now that big blue has its head out of its posterior things might be a little different as AMD risks a far greater hit or miss.

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Think AMD is on the right track still or reckon some serious changes need to be made in Shanghai or Sandtiger for them to stand a chance against Nehalem and future Intel Core processors? Share your thoughts in the forums.
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