Intel shows off Co-EMIB, ODI packaging tech

Intel has showcased new chip packaging technologies, including a combination of Embedded Multi-die Interconnect Bridge (EMIB) and Foveros on a single chip and a new interconnect technology it dubs Omni-Directional Interconnect (ODI).

Intel unveiled Foveros back in December 2018 as a three-dimensional chip packaging technology designed to allow more logic to be packed into a given footprint - an increase necessity given the company's continued delay in getting its 10nm node into volume production. Now, at the Semicon West convention for the semiconductor industry, the company has announced it has combined Foveros with its Embedded Multi-die Interconnect Bridge (EMIB).

Dubbed Co-EMIB, the combination of EMIB and Foveros - which has always been the company's plan for future products - allows for two or more Foveros elements to be connected with no loss of performance compared with a standard planar design. At the same time, chip designers are able to add additional 'tiles' for extra functionality - analogue circuitry and memory, for two examples - with high bandwidth and low power requirements.

At the same event, Intel also unveiled its new Omni-Directional Interconnect technology, designed to provide increased flexibility for communication between chiplets in a multi-layer package. Where EMIB allows for communication between chiplets in the same layer and Foveros with layers below, ODI supports both while increasing the size of the through-silicon vias (TSVs) used for inter-layer communication to provide increased power delivery, higher bandwidth, and lower latency. The company also showcased MDIO, an upgrade to its existing Advanced Interface Bus (AIB) with improved power efficiency and double the pin speed and bandwidth.

'Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip,' claims Babak Sabi, Intel corporate vice president for assembly and test technology development. 'A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors. Intel's vertically integrated structure provides an advantage in the era of heterogeneous integration, giving us an unmatched ability to co-optimise architecture, process and packaging to deliver leadership products.'

What Intel has not shared, however, is information on which products will be the first to use the new packaging technology, nor when they will arrive on shop shelves. It has previously set a target of the end of 2019 for production of a Lakefield part for ultra-mobile devices based on Foveros technology.