A leaked slide purporting to show Intel's roadmap for its Xeon family of server and high-performance computing processors, has offered a glimpse of the company's plans for the Skylake architecture.
Skylake is the name given to Broadwell's successor, itself the next processor generation after Intel's latest Haswell chips. Where Broadwell will merely be a simple process node shrink from 22nm to 14nm, retaining the same fundamental design as Haswell, Skylake is to be an evolution in architecture - and promises to introduce significant new features.
According to a slide leaked by a Polish university, removed by the site but not before German site PC Games Hardware was able to snag a copy, Intel's Skylake chips will include AVX 3.2, DDR4 and PCI Express 4.0 support among their improved feature set. The support for DDR4 will be of interest to performance enthusiasts, offering a new point-to-point design that allows for boosted clock frequencies and data transfer rates while running at a lower voltage than equivalent DDR3 memory.
While DDR4 is rumoured to be arriving on the desktop before Skylake, as part of Intel's Haswell-E enthusiast-grade processors, PCI Express 4.0 will be a first for the platform. Although a preliminary specification was released by industry consortium PCI-SIG back in 2011, the final specification isn't expected until 2014 or even 2015. Early drafts claimed that the standard will include double the transfer rate - 16 gigatransfers a second (GT/s) compared to 8GT/s - of PCIe 3.0, while also introducing new optimisations designed to reduce power draw during both idle and active states.
'Experts in the PCIe Electrical Workgroup carefully analysed a number of target bit rates for the next generation of PCIe architecture, taking into consideration several key factors including our ability to continue using low-cost materials,' claimed PCI-SIG chair Al Yanes at the time. 'We have concluded that 16GT/s is a feasible technical solution that satisfies our member companies’ requirements.'
The final feature announced on the slide is the introduction of AVX 3.2, the latest generation of Intel's Advanced Vector Extensions. Designed to build on the company's work on single instruction multiple data (SIMD) and streaming SIMD extensions (SSE), which allow the chip to perform a given instruction on multiple data simultaneously in order to improve performance, AVX 3.2 will replace the AVX 2 feature of Haswell and Broadwell. While Intel has yet to release details of AVX 3.2, it will likely result in similar improvements to AVX 2 - formerly known as the Haswell New Instructions. As with previous versions of AVX, however, it's not free performance: to take advantage of the new features, programmers will have to code and compile with AVX in mind.
The same slide also reveals a shift for Intel's Xeon Phi co-processor platform. The current Knights Corner PCIe add-in board, which contains 50 Pentium-style cores based on a 22nm process, will be succeeded by a 14nm version dubbed Knights Landing. The GDDR5 memory is to be replaced by lower-latency DDR4, but the big surprise is that the chip will also be made available in a socket format for the first time - allowing manufacturers to install Xeon Phi co-processors in high-performance computing systems alongside, rather than in the place of, graphics processing unit (GPU) based accelerator boards.
Intel, for its part, has refused to comment on the veracity of the slide or of any details surrounding Skylake. The platform itself is not expected to launch before 2016 at the earliest.
Skylake is the name given to Broadwell's successor, itself the next processor generation after Intel's latest Haswell chips. Where Broadwell will merely be a simple process node shrink from 22nm to 14nm, retaining the same fundamental design as Haswell, Skylake is to be an evolution in architecture - and promises to introduce significant new features.
According to a slide leaked by a Polish university, removed by the site but not before German site PC Games Hardware was able to snag a copy, Intel's Skylake chips will include AVX 3.2, DDR4 and PCI Express 4.0 support among their improved feature set. The support for DDR4 will be of interest to performance enthusiasts, offering a new point-to-point design that allows for boosted clock frequencies and data transfer rates while running at a lower voltage than equivalent DDR3 memory.
While DDR4 is rumoured to be arriving on the desktop before Skylake, as part of Intel's Haswell-E enthusiast-grade processors, PCI Express 4.0 will be a first for the platform. Although a preliminary specification was released by industry consortium PCI-SIG back in 2011, the final specification isn't expected until 2014 or even 2015. Early drafts claimed that the standard will include double the transfer rate - 16 gigatransfers a second (GT/s) compared to 8GT/s - of PCIe 3.0, while also introducing new optimisations designed to reduce power draw during both idle and active states.
'Experts in the PCIe Electrical Workgroup carefully analysed a number of target bit rates for the next generation of PCIe architecture, taking into consideration several key factors including our ability to continue using low-cost materials,' claimed PCI-SIG chair Al Yanes at the time. 'We have concluded that 16GT/s is a feasible technical solution that satisfies our member companies’ requirements.'
The final feature announced on the slide is the introduction of AVX 3.2, the latest generation of Intel's Advanced Vector Extensions. Designed to build on the company's work on single instruction multiple data (SIMD) and streaming SIMD extensions (SSE), which allow the chip to perform a given instruction on multiple data simultaneously in order to improve performance, AVX 3.2 will replace the AVX 2 feature of Haswell and Broadwell. While Intel has yet to release details of AVX 3.2, it will likely result in similar improvements to AVX 2 - formerly known as the Haswell New Instructions. As with previous versions of AVX, however, it's not free performance: to take advantage of the new features, programmers will have to code and compile with AVX in mind.
The same slide also reveals a shift for Intel's Xeon Phi co-processor platform. The current Knights Corner PCIe add-in board, which contains 50 Pentium-style cores based on a 22nm process, will be succeeded by a 14nm version dubbed Knights Landing. The GDDR5 memory is to be replaced by lower-latency DDR4, but the big surprise is that the chip will also be made available in a socket format for the first time - allowing manufacturers to install Xeon Phi co-processors in high-performance computing systems alongside, rather than in the place of, graphics processing unit (GPU) based accelerator boards.
Intel, for its part, has refused to comment on the veracity of the slide or of any details surrounding Skylake. The platform itself is not expected to launch before 2016 at the earliest.
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