RISC-V Foundation ratifies ISA specifications

The RISC-V Foundation has announced a milestone for the burgeoning processor architecture: The ratification of the base instruction set architecture (ISA) and privileged architecture specifications.

First developed at the University of California at Berkeley in 2010, RISC-V is a reduced instruction set computing (RISC) instruction set architecture (ISA) with a difference: It is made available not only royalty-free but under a permissive licence, allowing anyone to both build parts based on the ISA and to modify the ISA as required for their own needs. With an ISA licence for Arm costing somewhere in the millions of pounds and licences for x86 being entirely unavailable unless you're one of the handful of companies who got in early enough, it's a tempting proposition: Western Digital has begun transitioning its storage processing products to RISC-V using its in-house open-source SweRV Core implementation, Nvidia is beginning to make the move after switching to RISC-V for its logic cores, Rambus has picked the ISA for its latest crypto products, and it can be found everywhere from deep-learning accelerators to SSD controllers, as well as development boards capable of booting mainstream Linux.

All these have one thing in common, however: They are effectively based on an unratified version of the RISC-V ISA specification, meaning it was always possible - though unlikely - that the not-for-profit RISC-V Foundation might choose to modify the specification in a way that would make future RISC-V parts incompatible with what has come before. With SiFive chief executive Naveed Sherwani predicting commercial RISC-V smartphones within two years and servers in five, that's a problem - but one the Foundation has now solved with formal ratification of the specification.

'RISC-V was designed with a simple fixed base ISA and modular fixed standard extensions to help prevent fragmentation while also supporting customisation,' explains Krste Asanović, chair of the RISC-V Foundation board. 'The RISC-V ecosystem has already demonstrated a large degree of interoperability among various implementations. Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever.'

The ratification locks in the both the base ISA standard as well as the privileged architecture specification, designed to provide protection between different levels of the software stack and prevent unprivileged code from interfering with that running at a higher level. 'The RISC-V privileged architecture serves as a contract between RISC-V hardware and software such as Linux and FreeBSD. Ratifying these standards is a milestone for RISC-V,' explains Andrew Waterman, chair of the RISC-V Privileged Architecture Task Group. 'Operating system developers and hardware vendors can build to these specs with confidence that their work will be compatible.'

The ratified specifications are available now on the RISC-V Foundation website.