Western Digital unveils open-source SweRV RISC-V core

Western Digital has lifted the lid on its first in-house processor, the RISC-V-based SweRV Core, which it is to release under an open source licence.

That Western Digital has been playing with the open RISC-V instruction set architecture (ISA), using which anyone can produce a processor design without paying a penny in royalties or licensing fees, is no secret: Back in 2017 the company pledged to switch to RISC-V in its storage processing products with a view to shipping a billion cores over the following two years. It's not alone, either: Nvidia has begun transitioning away from proprietary cores to RISC-V to drive input/output in its graphics products, Rambus uses RISC-V in security parts, and it has even found its way into SSD storage controllers.

'As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,' explains Western Digital chief technology officer Martin Fink of his company's interest in the ISA. 'Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realised by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.'

The SweRV core itself is a two-way superscalar implementation of the 32-bit variant of the RISC-V ISA featuring a nine-stage pipeline capable of loading multiple instructions for simultaneous in-order execution. Implemented, at present, on a 28nm CMOS process node, the core runs at up to 1.8GHz and achieves a claimed estimated performance of 4.9 CoreMarks per megahertz.

In the spirit of the RISC-V movement, Western Digital has confirmed it plans to not only use SweRV in its own products but to release it under an open-source licence. It has already done so with two supporting technologies: The SweRV Instruction Set Simulator (ISS), through which interested parties can test the core; and OmniXtend, which implements cache coherent memory over an Ethernet fabric targeting everything from CPUs to GPUs and machine learning co-processors.

The SweRV core itself is to be released in the first quarter of 2019, Western Digital has confirmed. More information on the company's RISC-V programmes can be found on the official website.