PCI-SIG - the Peripheral Component Interconnect Special Interests Group - has announced that it has finalised PCI Express 4.0 and has pencilled its replacement, unsurprisingly dubbed PCI Express 5.0, for release in 2019.
Designed to take over from the existing PCI Express 3.x family of standards, PCI Express 4.0 promises a doubling of the available bandwidth: Where PCIe 3.0 tops out at eight gigatransfers per second (GT/s), 8Gb/s of link bandwidth per lane, and therefore a peak of 32GB/s bandwidth per 16-lane slot, PCIe 4.0 offers 16GT/s and 16Gb/s of link bandwidth for a peak of 64GB/s per 16-lane slot. These figures, though, are the theoretical maximum supported by the standard and not necessarily the rates users will see in the wild. This improvement in raw throughput is joined, the PCI-SIG claims, by extended lane-width configurations for increased flexibility, lower minimum speeds for low-power operation, latency reductions, and boosted scalability.
While PCIe 4.0 has yet to appear commercially, PCI-SIG is already hard at work on its successor PCIe 5.0 and has already released a preliminary third revision to its member companies. 'In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,' claimed Al Yanes, PCI-SIG chair and president, at the announcement. 'PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.'
As well as a further doubling of bandwidth over PCIe 4.0 to a peak of 128GB/s, PCI-SIG claims PCIe 5.0 will offer improvements that will suit 'constricted form factor applications needing to increase channel width', meaning it's taking aim at both the high-performance market with the promise of boosted network, storage, and accelerator performance and the embedded and low-power market.
No formal release date has been offered for PCIe 5.0, but PCI-SIG has indicated it expects to finalise the standard some time in 2019.
Designed to take over from the existing PCI Express 3.x family of standards, PCI Express 4.0 promises a doubling of the available bandwidth: Where PCIe 3.0 tops out at eight gigatransfers per second (GT/s), 8Gb/s of link bandwidth per lane, and therefore a peak of 32GB/s bandwidth per 16-lane slot, PCIe 4.0 offers 16GT/s and 16Gb/s of link bandwidth for a peak of 64GB/s per 16-lane slot. These figures, though, are the theoretical maximum supported by the standard and not necessarily the rates users will see in the wild. This improvement in raw throughput is joined, the PCI-SIG claims, by extended lane-width configurations for increased flexibility, lower minimum speeds for low-power operation, latency reductions, and boosted scalability.
While PCIe 4.0 has yet to appear commercially, PCI-SIG is already hard at work on its successor PCIe 5.0 and has already released a preliminary third revision to its member companies. 'In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,' claimed Al Yanes, PCI-SIG chair and president, at the announcement. 'PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.'
As well as a further doubling of bandwidth over PCIe 4.0 to a peak of 128GB/s, PCI-SIG claims PCIe 5.0 will offer improvements that will suit 'constricted form factor applications needing to increase channel width', meaning it's taking aim at both the high-performance market with the promise of boosted network, storage, and accelerator performance and the embedded and low-power market.
No formal release date has been offered for PCIe 5.0, but PCI-SIG has indicated it expects to finalise the standard some time in 2019.
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