Researchers boost performance with Clairvoyance

A team of computer researchers have unveiled Clairvoyance, a compiler technique for improving the performance of low-end simple out-of-order (OoO) execution based processors - and claim it can boost selected workloads by as much as 43 percent.

Researchers from the National University of Singapore, Uppsala University, Norwegian University of Science and Technology, and the KTH Royal Institute of Technology have claimed that today's complex out-of-order processors are designed around one core concept: the steady improvement of performance at the cost of 'radically increased design complexity and wasteful energy consumption'. This, the team claims, gives complex OoO processors - like mainstream PC chips - considerable advantages in performance over simpler OoO designs, with the Arm-based Hewlett Packard Moonshot m400 and AMD Opteron A1100 families name-checked as being under-performing in memory-bound applications.

The answer, the researchers claim, is Clairvoyance. 'Clairvoyance builds upon techniques such as software pipelining, program slicing, and decoupled access-execute and generates code that exhibits improved memory-level parallelism (MLP) and instruction-level parallelism (ILP). For this, Clairvoyance prioritises the execution of critical instructions, namely loads, and identifies independent instructions that can be interleaved between loads and their uses.'

Using a range of benchmarks, the team were able to demonstrate that Clairvoyance - which is a purely software-based optimisation in the compiler, requiring no hardware modification to operate - increased both memory- and instruction-level parallelism, leading to a 14 percent geometric mean improvement in the performance of memory-bound benchmarks and an overall improvement of up to 43 percent for selected workloads.

If Clairvoyance can prove itself out of the world of benchmarks, it could be the shot in the arm that the effort to get Arm-based processors into the data centre has been needing. Full details are available in the team's paper (PDF warning), which was published in the April edition of the 'IEEE Transactions on Computers' journal.