The Secrets of PC Memory: Part 4

Written by Ryan J. Leng

February 10, 2008 | 07:39

Tags: #ddr3

Companies: #crucial

Reset Function

DDR3 introduced an Asynchronous Reset function which is initiated externally by the memory controller. The Reset signal will force DRAMs into a well defined non-operational state. This is an understated, yet extremely critical feature.

The Reset function clears all status and data in the DRAMs without the need to individually reset each one or power down the module. This saves time and power when the memory controller attempts to bring the memory to a known state. Once the Reset has been activated, the memory will completely re-initialise and the Reset can be activated at any time during any cycle.

During the memory start-up power ramp, Reset is activated until the memory power has reached a stable condition – this ensures the subsequent calibration is not based on unreliable power status. Reset works hand-in-hand with ZQ Calibration and at any cycle, once the Reset function has been activated, ZQ Calibration Long (ZQCL) will come into play. This will make sure timing accuracy and signal quality are in the best possible shape before the data transfer begins.

This feature has been discussed and requested by some memory designers many times at JEDEC but it wasn’t until DDR3 where the availability of DRAM pins without any specific assignment has made the Reset feature possible.

The Secrets of PC Memory: Part 4 The Challenges facing DDR3 and beyond

The Challenges facing DDR3 and beyond

During the 2007 Electronics Design Convention, DesignCon; Altera Corporation presented a paper on calibration techniques and the condition of DDR memory in the near future. It states that “even though memory performances double with every generation, the memory uncertainties do not decrease at the same rate.

We recently asked Micron Technology about the challenges in designing for DDR3 at 1,600MHz and beyond. Application Engineer, Aaron Boehm states that “it is getting more and more difficult with each generation of DRAM because we continue to shrink our die, the speeds go up and the voltage goes down. It is just a lot harder to get clean signals both internal and external to the DRAM. The bus architecture is challenging and the closer you’re running signals together, the more problems you have with crosstalk.

Boehm continued to stress that, “with reduced voltages, it is hard to get good clean signalling edges. So I think as we move forward, it becomes more and more challenging to meet these speeds.” Fundamentally, when the memory speed increases, there are smaller margins to work with.

The memory system is a combination of memory modules, the motherboard and the CPU. Computer memory system cannot be regarded only as just one part at a time, but instead, inclusive of the entire memory sub-system on the mainboard. Therefore, memory performance and overclocking is highly dependent on all these components working perfectly under tighter and tighter tolerances.

This poses a new problem for DRAM and memory module manufacturers: as memory speed increases, attaining component compatibility becomes more and more difficult, “...especially when you have a wide variety of motherboard designs out there. It is very difficult as you’re trying to play in an environment where you have no control in a lot of the cases. Even though they want to go extremely fast, they are trying to cut cost in the PCB or the motherboard,” Boehm cautioned.

What was expected and we’ve already seen happening is the diminishing overclocking returns with each generation of DDR technology – is it finally time for a revolutionary change in the memory industry, as opposed to evolving to DDR4? That is something we don’t know the answer to at the moment...
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