Researchers at the National Taiwan University have proposed a novel new error correction cache for solid-state drives (SSDs) which is claimed could improve read performance considerably.
The majority of high-capacity solid-state storage on the market today uses NAND flash technology, which is both affordable and responsive. However, they can be prone to errors owing to each cell of the NAND flash device having a limited number of write cycles before it falls over. To compensate, SSDs put aside a number of 'spare' cells to map failed cells to, using error detection and correction code to determine when a cell has failed and to recover its data for writing to the new cell.
It's a process that works well, but one which introduces a bottleneck in the performance of the SSD. A team of researchers at the National Taiwan University led by Ren-Shuo Liu targeted a particular type of error correction code, low-density parity check (LDPC), and worked to mitigate this bottleneck. The result: error-correcting cache, or EC-Cache.
As detailed in a paper due to be published in an upcoming issue of the IEEE Transactions on Computers journal, the team found that they could exploit 'error locality' - the tendency for the majority of read errors to occur at the same positions until a given NAND flash 'page' is erased - to reduce the decoding overhead of LDPC. Under simulation, the EC-Cache technology was proved to improve the read performance of SSDs that use LDPC by a ratio of 2:6.
Thus far, Liu's team has not indicated whether or not there has been interest from any SSD vendors in implementing the EC-Cache technology into future generations of their products. If the team's performance claims ring true, and the technology can be implemented inexpensively in existing NAND flash controllers, it is likely to be adopted sooner rather than later - but a lack of the technology is certainly not something that should put you off an SSD purchase in the next year or two.
A preprint copy of the team's paper is available at the IEEE Computer Society website.
The majority of high-capacity solid-state storage on the market today uses NAND flash technology, which is both affordable and responsive. However, they can be prone to errors owing to each cell of the NAND flash device having a limited number of write cycles before it falls over. To compensate, SSDs put aside a number of 'spare' cells to map failed cells to, using error detection and correction code to determine when a cell has failed and to recover its data for writing to the new cell.
It's a process that works well, but one which introduces a bottleneck in the performance of the SSD. A team of researchers at the National Taiwan University led by Ren-Shuo Liu targeted a particular type of error correction code, low-density parity check (LDPC), and worked to mitigate this bottleneck. The result: error-correcting cache, or EC-Cache.
As detailed in a paper due to be published in an upcoming issue of the IEEE Transactions on Computers journal, the team found that they could exploit 'error locality' - the tendency for the majority of read errors to occur at the same positions until a given NAND flash 'page' is erased - to reduce the decoding overhead of LDPC. Under simulation, the EC-Cache technology was proved to improve the read performance of SSDs that use LDPC by a ratio of 2:6.
Thus far, Liu's team has not indicated whether or not there has been interest from any SSD vendors in implementing the EC-Cache technology into future generations of their products. If the team's performance claims ring true, and the technology can be implemented inexpensively in existing NAND flash controllers, it is likely to be adopted sooner rather than later - but a lack of the technology is certainly not something that should put you off an SSD purchase in the next year or two.
A preprint copy of the team's paper is available at the IEEE Computer Society website.
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